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VLSI Projects

VLSI Projects in Chennai

Wiztech Automation, Anna Nagar, Chennai, has been in the training arena for the last 10 years offering professional diploma and advance diploma courses apart from the Certification programs in Industrial Automation based domains (PLC, SCADA, DCS, HMI, VFD) and also VLSI, Embedded Systems, IT, Designing & Web designing etc.

Final Year projects for engineering students is a special area in which Wiztech Automation has invested huge time and energy and today Final Year VLSI Projects is one area in which Wiztech is involved in a big way. The increase in number of students steadily indicates the quality, innovation, time bounded and budget based nature of the projects that Wiztech handles. Wiztech Automation's last 10 years organizational history reveals that the organization grew through its qualitative nature of services and the delivery-in-time-commitments matching with the affordability of the students. Today Wiztech Automation earned a distinct name for itself being a front-line service provider-organization in regard to the Final Year Projects. Students with diverse-domain project requirements approach Wiztech considering the infrastructure, facilities and the well trained and experienced faculty team of trainers. Students looking for their requirements of any nature in VLSI projects could approach Wiztech to attain excellence.



VLSI Projects - Front End Design

 
S.No Code VLSI IEEE 2016 Project Titles Year Abstract
01
WSV0010
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code(IEEE 2016)
2016
02
WSV0009
Single-Port SRAM-Based Transpose Memory with Diagonal Data Mapping for Large Size 2-D DCT/IDCT(IEEE 2016)
2016
03
WSV0008
RTL Design and VLSI Implementation of an efficient Convolutional Encoder and Adaptive Viterbi Decoder(IEEE 2016)
2016
04
WSV0007
Fast Radix-10 Multiplication Using Redundant BCD Codes(IEEE 2016)
2016
05
WSV0006
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block(IEEE 2016)
2016
06
WSV0005
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability(IEEE 2016)
2016
07
WSV0004
An Optimized Modified Booth Re-coder for Efficient Design of the Add-Multiply Operator(IEEE 2016)
2016
08
WSV0003
Design and Analysis of Approximate Compressors for Multiplication(IEEE 2016)
2016
09
WSV0002
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations(IEEE 2016)
2016
10
WSV0001
High-Performance Hardware Implementation for RC4 Stream Cipher(IEEE 2016)
2016

VLSI Projects - CMOS Design

 
S.No Code VLSI IEEE 2016 Project Titles Year Abstract
01
WCV0005
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic(IEEE-2016)
2016
02
WCV0004
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree(IEEE-2016)
2016
03
WCV0003
Recursive Approach to the Design of a Parallel Self-Timed Adder(IEEE-2016)
2016
04
WCV0002
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme(IEEE-2016)
2016
05
WCV0001
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator(IEEE-2016)
2016

VLSI Projects Front End Design and CMOS Design

 
S.No Code VLSI IEEE 2016 Project Titles Year Abstract
01
VL0050
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
2016
02
VL0049
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
2016
03
VL0048
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
2016
04
VL0047
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only
2016
05
VL0046
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
2016
06
VL0045
An Efficient De noising Architecture for Removal of Impulse Noise in Images
2016
07
VL0044
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
2016
08
VL0043
Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box
2016
09
VL0042
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique
2016
10
VL0041
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
2016
11
VL0040
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
2016
12
VL0039
A Low-Power Single-Phase Clock Multiband Flexible Divider
2016
13
VL0038
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
2016
14
VL0037
A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers
2016
15
VL0036
Separable Reversible Data-Hiding of Image
2016
16
VL0035
Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques
2016
17
VL0034
Accumulator Based 3-Weight Pattern Generation
2016
18
VL0033
On Modulo2^n+1 Adder Design
2016
19
VL0032
Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error
2016
20
VL0031
High-Speed Architectures for Multiplication Using Reordered Normal Basis
2016
21
VL0030
FFT Implementation with Fused Floating-Point Operations
2016
22
VL0029
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications
2016
23
VL0028
An Efficient TCAM-Based Implementation of Multi-pattern Matching Using Covered State Encoding
2016
24
VL0027
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
2016
25
VL0026
Low-Power and Area-Efficient Carry Select Adder
2016
26
VL0025
Word-Level Finite Field Multiplier Using Normal Basis
2016
27
VL0024
BIST-Based Fault Diagnosis for Read-Only Memories
2016
28
VL0023
VLSI Characterization of the Cryptographic Hash Function BLAKE
2016
29
VL0022
Efficient Design of a Hybrid Adder Using Quantum-Dot Cellular Automata
2016
30
VL0021
Radix-8 Booth Encoded Modulo 2^n-1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System
2016
31
VL0020
An Efficient Implementation of Floating Point Multiplier
2016
32
VL0019
Memory Efficient Modular VLSI Architecture for High throughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT
2016
33
VL0018
Adiabatic Technique for Energy Efficient Logic Circuits Design
2016
34
VL0017
SET D-Flip Flop Design for Portable Applications
2016
35
VL0016
Reducing the Computation Time in (Short Bit-Width) Two’s Complement Multipliers
2016
36
VL0015
Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops
2016
37
VL0014
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
2016
38
VL0013
Efficient Pattern Matching Algorithm for Memory Architecture
2016
39
VL0012
Design of Sequential Elements for Low Power Clocking System
2016
40
VL0011
Design of Fixed-Width Multipliers With Linear Compensation Function
2016
41
VL0010
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
2016
42
VL0009
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
2016
43
VL0008
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique
2016
44
VL0007
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters
2016
45
VL0006
A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
2016
46
VL0005
Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT
2016
47
VL0004
Hardware Implementation of RFID Mutual Authentication Protocol
2016
48
VL0003
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
2016
49
VL0002
Self-Test Techniques for Crypto-Devices
2016
50
VL0001
Bit-Swapping LFSR and Scan-Chain Ordering : A Novel Technique for Peak and Average Power Reduction in Scan-Based BIST
2016


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